The present invention relates to an on die thermal sensor (ODTS) used in various semiconductor devices, and more particularly, to an ODTS under low power condition.
An application of an ODTS to a dynamic random access memory (DRAM), one of the semiconductor devices, will be described below. A DRAM cell consists of one switching transistor and one storage capacitor. Data state (logic HIGH or logic LOW) of the DRAM cell is determined by whether the storage capacitor is charged or discharged, that is, whether the terminal voltage of the storage capacitor is high or low.
Since data is stored in such a way that charges are accumulated in the capacitor, power consumption does not occur in principle. The data, however, may be lost because leakage current caused by PN junction of a metal-oxide semiconductor (MOS) transistor reduces an amount of charges stored initially. In order to prevent the data loss, the data of the DRAM cell is read before the data is lost, and a normal amount of charge is recharged according to the read data.
In other words, the data can be retained by repeating the read operation and the recharge operation periodically. The operation of recharging the cell charges is referred to as a refresh operation. The refresh operation is controlled by a DRAM controller. Due to the refresh operation, the DRAM dissipates refresh power. The reduction of power consumption is an important and critical issue in a battery operated system requiring lower power consumption.
One of many attempts to reduce power consumption in the refresh operation is to change a refresh period according to temperature. As the temperature is lower, the data retention time in the DRAM becomes longer. Based on this characteristic, the power consumption can be reduced by dividing a temperature region into a plurality of sub-regions and relatively reducing a refresh clock frequency at a low temperature region. Therefore, there is a demand for a device that can correctly detect the internal temperature of the DRAM and output information about the detected temperature.
In addition, as the integration level and operating speed are increasing, a large amount of heat is generated from the DRAM itself. Because the generated heat increases the internal temperature of the DRAM, the DRAM may be abnormally operated or damaged. Therefore, there is a demand for a device that can correctly detect the internal temperature of the DRAM and output information about the detected temperature.
FIG. 1 is a block diagram of a conventional ODTS.
Referring to FIG. 1, the conventional ODTS includes a bandgap unit 10, a tracking unit 20, and a control unit 30. The bandgap unit 10 includes a temperature detector 11 and a trimmer 12, and the tracking unit 20 includes a voltage comparator 21, a counter 22 and a converter 23. The control unit 30 controls the operation of the ODTS.
Specifically, the temperature detector 11 detects a temperature of a semiconductor device using the fact that a base-emitter voltage (VBE) change of a bipolar junction transistor (BJT) is about −1.8 mV/° C. in a bandgap circuit, which is not influenced by the change of temperature or power supply voltage of the semiconductor device. The temperature detector 11 outputs a first voltage VTEMP corresponding to the temperature by 1:1 amplifying the finely changing base-emitter voltage (VBE) of the BJT. That is, as the temperature of the semiconductor device is higher, the temperature detector 11 outputs a lower base-emitter voltage (VBE) of the BJT.
The converter 23 is implemented with a digital-to-analog converter (DAC). The converter 23 outputs a second voltage DACOUT in response to a temperature control code output from the counter 22. The second voltage DACOUT is an analog value and the temperature control code is a digital value. The second voltage DACOUT is determined by a maximum variation voltage VULIMIT and a minimum variation voltage VLLIMIT output from the trimmer 12.
The voltage comparator 21 compares the first voltage VTEMP and the second voltage DACOUT. When the first voltage VTEMP is lower than the second voltage DACOUT, the voltage comparator 21 outputs a decrement signal DEC to cause the counter 22 to decrease a preset digital code. On the other hand, when the first voltage VTEMP is higher than the second voltage DACOUT, the voltage comparator 21 outputs an increment signal INC to cause the counter 22 to increase the preset digital code.
In addition, the counter 22 increases or decreases the preset digital code in response to the increment signal INC or the decrement signal DEC output from the voltage comparator 21, and outputs the temperature control code containing temperature information.
The trimmer 12 receives a reference voltage VREF from the bandgap circuit that is not influenced by the change of the temperature or power supply voltage of the semiconductor device, and outputs the maximum variation voltage VULIMIT and the minimum variation voltage VLLIMIT that are not influenced by the change of the temperature or power supply voltage of the semiconductor device. In the manufacturing process of the semiconductor device, the range of the base-emitter voltage (VBE) of the BJT with respect to temperature is different in each die. Therefore, the potential level of the reference voltage VREF is previously set through an external circuit in order to increase the accuracy of temperature compensation. The maximum variation voltage VULIMIT and the minimum variation voltage VLLIMIT have a constant voltage difference.
Through the operation of the bandgap unit 10 and the tracking unit 20, the second voltage DACOUT tracks the first voltage VTEMP and then the digital code stored in the counter 22 becomes a digital code representing current temperature information.
The control unit 30 controls the bandgap unit 10 and the tracking unit 20. Specifically, the control unit 30 outputs an ODTS enable signal ODTS_ON to enable the bandgap unit 10 and outputs a first enable signal ADC_EN_OLD to control the tracking unit 20.
The first enable signal ADC_EN_OLD output from the control unit 30 is activated to a logic high level for a preset time, e.g., 30 μs, after the bandgap unit 10 is enabled in response to the ODTS enable signal ODTS_ON, and then is deactivated to a logic low level. In other words, the tracking unit 20 operates while the first enable signal ADC_EN_OLD is in the activated state, and is disabled automatically.
FIG. 2 is a graph showing current consumption of the ODTS of FIG. 1.
Referring to FIG. 2, the ODTS consumes a large amount of current during the period in which the tracking unit 20 operates in response to the first enable signal ADC_EN_OLD of a logic high level. Therefore, the conventional ODTS has a problem in that it consumes a large amount of current as the operation period of the tracking unit 20 becomes longer.